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<title>antcc/amd64/sysv.c, branch trunk</title>
<subtitle>A little C compiler</subtitle>
<id>https://git.lemon.rip/antcc/atom?h=trunk</id>
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<updated>2025-12-12T16:40:35+00:00</updated>
<entry>
<title>s/amd64/x86_64/</title>
<updated>2025-12-12T16:40:35+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-12-12T16:40:35+00:00</published>
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<id>urn:sha1:24bcc929477751b056e81e7772dc2bb3d11ce4a5</id>
<content type='text'>
</content>
</entry>
<entry>
<title>rename arraylength macro -&gt; countof</title>
<updated>2025-12-11T19:43:24+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-12-11T19:43:24+00:00</published>
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<id>urn:sha1:88652eeb10cd9381aafb2d55e9474bb0799630b1</id>
<content type='text'>
</content>
</entry>
<entry>
<title>abi: fix aggregate passed by regs 2nd reg offset</title>
<updated>2025-12-06T17:59:53+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-12-06T17:59:53+00:00</published>
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<id>urn:sha1:f7d68175fc2b52230b8f78bf78145c7f1d0ad9c5</id>
<content type='text'>
It was broken for example `struct { i32 a; f64 b; }` (would try to
load/store b from byte offset 4, not 8). Introduce r2off, realize in
x86-64 it's always 8; even `struct {i32 a; f32 b;}` gets passed in one
(integer) register. But not so in (future) ABIs like RISC-V, I believe
there `{i32, f32}` would get passed in 1 integer and 1 float register
(r2off = 4).
</content>
</entry>
<entry>
<title>add command-line predefined macros (-D, -U)</title>
<updated>2025-12-06T10:55:41+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-12-06T10:41:44+00:00</published>
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<id>urn:sha1:d82f3052c813f671561362126d0fbe08568542d3</id>
<content type='text'>
</content>
</entry>
<entry>
<title>amd64: va_arg for small aggregates</title>
<updated>2025-11-23T16:10:30+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-23T16:10:30+00:00</published>
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<id>urn:sha1:bd3307a3e98e75b7cce5aa130719022a00323e0f</id>
<content type='text'>
</content>
</entry>
<entry>
<title>implement float varargs, and some other fixes</title>
<updated>2025-11-23T14:29:55+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-23T11:02:27+00:00</published>
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<id>urn:sha1:1f72464c6451fcff16180d00af537225acc9b83c</id>
<content type='text'>
</content>
</entry>
<entry>
<title>sysv: nested scalar classification of struct shouldn't return KPTR, used to indicate aggregate in the stack</title>
<updated>2025-11-22T12:25:07+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-22T12:25:07+00:00</published>
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<id>urn:sha1:6256bc1d0485a74e7d6728c95603a54a4149cb64</id>
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</content>
</entry>
<entry>
<title>change op names to match 285063eba44</title>
<updated>2025-11-21T15:49:53+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-21T15:49:53+00:00</published>
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<id>urn:sha1:ec4cfe9db9afc1d1c633a922174f5bb0685b0c32</id>
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</content>
</entry>
<entry>
<title>rename IR classes to reflect bitsize</title>
<updated>2025-11-21T10:03:23+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-21T10:03:23+00:00</published>
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<id>urn:sha1:285063eba442e2a8ac29fd42e0d17d996bcc5d00</id>
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</content>
</entry>
<entry>
<title>sysv: document vaargs stack layout stuff</title>
<updated>2025-11-14T18:23:18+00:00</updated>
<author>
<name>lemon</name>
<email>lsof@mailbox.org</email>
</author>
<published>2025-11-14T18:23:18+00:00</published>
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<id>urn:sha1:57223ba45c4a88003826d25557a965d208c28639</id>
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