antcc/amd64, branch trunk A little C compiler https://git.lemon.rip/antcc/atom?h=trunk 2025-12-12T16:40:35+00:00 s/amd64/x86_64/ 2025-12-12T16:40:35+00:00 lemon lsof@mailbox.org 2025-12-12T16:40:35+00:00 urn:sha1:24bcc929477751b056e81e7772dc2bb3d11ce4a5 emit: turn ADD -imm into SUB imm 2025-12-12T11:04:38+00:00 lemon lsof@mailbox.org 2025-12-12T11:04:38+00:00 urn:sha1:3cd8e39ff61217a37b41cee47f2682f5291317d6 isel: fix bug where sub turned into add, but inplace didn't reflect 2025-12-12T10:54:53+00:00 lemon lsof@mailbox.org 2025-12-12T10:54:53+00:00 urn:sha1:53be85354860d39e15208ad765fbc3d373369a3d amd64/emit: change instr desc table a little 2025-12-12T09:46:55+00:00 lemon lsof@mailbox.org 2025-12-12T09:46:55+00:00 urn:sha1:8b5570c855d58ea75d991d027040eb351ffadb80 rename arraylength macro -> countof 2025-12-11T19:43:24+00:00 lemon lsof@mailbox.org 2025-12-11T19:43:24+00:00 urn:sha1:88652eeb10cd9381aafb2d55e9474bb0799630b1 parallel move; implement reg<->stack swp 2025-12-10T20:16:54+00:00 lemon lsof@mailbox.org 2025-12-10T20:16:54+00:00 urn:sha1:97882e8d32fd99e1edaf5361bfd3b6852dbb1a3d misc fixes 2025-12-10T08:57:22+00:00 lemon lsof@mailbox.org 2025-12-10T08:57:22+00:00 urn:sha1:15cf067c4e65c1728c48ab049d48219daa436265 amd64: fix wrong condition code being used for float gth 2025-12-07T11:32:51+00:00 lemon lsof@mailbox.org 2025-12-07T11:32:51+00:00 urn:sha1:66a58cee57b5b3025d441d84e9e0b1df2885118e ughh amd64: use XORPS for floating point negation 2025-12-07T11:29:27+00:00 lemon lsof@mailbox.org 2025-12-07T11:29:27+00:00 urn:sha1:4d4e61e82cd693d2800bf409c8e3dde1ac2b75a5 Previously `neg x` was being turned into `sub 0, x`. But this gives the wrong result for zero/negative zero (-0.0 == -0.0 but 0.0 - 0.0 == 0.0), so it wasn't IEEE compliant or correct. Do what every other compiler does instead and flip the sign bit with an exclusive or. Should implement someway of deduplicating small data constants like the ones used here though. abi: fix aggregate passed by regs 2nd reg offset 2025-12-06T17:59:53+00:00 lemon lsof@mailbox.org 2025-12-06T17:59:53+00:00 urn:sha1:f7d68175fc2b52230b8f78bf78145c7f1d0ad9c5 It was broken for example `struct { i32 a; f64 b; }` (would try to load/store b from byte offset 4, not 8). Introduce r2off, realize in x86-64 it's always 8; even `struct {i32 a; f32 b;}` gets passed in one (integer) register. But not so in (future) ABIs like RISC-V, I believe there `{i32, f32}` would get passed in 1 integer and 1 float register (r2off = 4).