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* amd64/isel: fix addressing index shift being possibly too large to encode (duh) lemon2025-11-291-1/+1
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* isel: fix branch arg lemon2025-11-271-0/+2
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* abi/isel: aggregate args in stack wip lemon2025-11-271-6/+11
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* fix regression w/ store instr + memory immediate lemon2025-11-241-11/+13
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* isel: loadstoreaddr don't fuseaddr as much lemon2025-11-241-3/+5
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* implement float varargs, and some other fixes lemon2025-11-231-0/+6
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* amd64/isel: indirect call arg must be memaddr lemon2025-11-221-2/+7
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* make sure indirect function call pointer does not end up in clobber reg lemon2025-11-221-0/+5
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* ir: barebones IR passes checked contracts lemon2025-11-211-0/+2
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* remove umul lemon2025-11-211-3/+2
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* change op names to match 285063eba44 lemon2025-11-211-13/+13
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* rename IR classes to reflect bitsize lemon2025-11-211-11/+11
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* isel: lower allocas a different way, such that stk address gets materialized ↵ lemon2025-11-201-23/+58
| | | | when necesary
* ir: for easier debugging, keep ctype in dats, print as literal when possible lemon2025-11-201-3/+7
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* debug output to stdout lemon2025-11-191-1/+1
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* isel: don't incorrectly clamp constant lhs of shift operation lemon2025-11-151-4/+4
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* isel: fold arith lemon2025-11-141-1/+21
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* preeliminary va_list support lemon2025-11-141-5/+23
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* amd64/isel: fold Oext with immediates lemon2025-11-121-0/+8
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* implement argument passing in stack lemon2025-11-121-6/+18
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* fixup! amd64: get rid of xinc/xdec. handle those at emit stage lemon2025-11-091-1/+1
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* amd64/isel: make `sub imm` work for address fusing lemon2025-11-091-2/+8
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* amd64: get rid of xinc/xdec. handle those at emit stage lemon2025-11-091-18/+1
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* amd64: fix aggregate abi stuff;; ir: fold, peephole optimizing constructors lemon2025-11-051-2/+1
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* isel: fix 3-address add when used for flags in branch lemon2025-11-021-0/+3
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* isel fixes lemon2025-10-301-3/+11
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* isel: fix address sel for absolute int addr lemon2025-10-261-0/+7
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* amd64 missing stuff lemon2025-10-231-2/+10
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* isel: fix -fpic factoring out non-symbolic address operands lemon2025-10-231-1/+1
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* amd64: load/store from abs address constants; movabs lemon2025-10-231-10/+19
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* amd64: float conversion insntrs lemon2025-10-181-0/+13
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* small thigns lemon2025-10-181-1/+1
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* bugfixes lemon2025-10-101-0/+1
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* initial implementation of run-time array/aggregate initializers lemon2025-10-081-0/+4
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* fix some more codegen bugs for symbol constants lemon2025-09-161-2/+5
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* codegen: float cmp, ior; frontend: fix cond expr bug lemon2025-09-141-2/+5
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* preliminary pie and pic lemon2025-09-141-8/+25
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* amd64: fix isel for numeric conversion ops lemon2023-08-071-4/+4
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* amd64 codegen fixes lemon2023-07-071-1/+1
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* misc bugfixs lemon2023-06-301-4/+2
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* add initializers (only static for initialier list rn) lemon2023-06-291-7/+33
| | | | and other fixes
* fix some warnings lemon2023-06-251-9/+1
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* fix regalloc thinking some ins are dead by adding ins.keep lemon2023-06-241-1/+5
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* amd64/emit: more float fixes lemon2023-06-241-21/+24
| | | | | optimize loading 0.0 in phis as well as regular copies and also don't use inc or addr for float addition
* backend: fix regalloc to work with more complex dataflow lemon2023-06-241-1/+1
| | | | | | | | basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes
* change RMORE -> RADDR; use RXXX (RNONE) for special args,also undef lemon2023-06-221-12/+12
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* explicitly store predecessors in each block lemon2023-06-211-4/+4
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* amd64: conform to ABI for varargs func calls lemon2023-06-201-1/+0
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* improve codegen for div a little (bikeshedding) lemon2023-06-201-0/+5
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* fix regression wiht ret args not being fixed lemon2023-06-201-2/+7
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