| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | fix edge case codegen bugs (w/ stack offsets, spilling) | 2025-10-22 | 1 | -0/+2 | |
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| * | amd64/emit errata | 2025-10-20 | 1 | -1/+1 | |
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| * | Organize source files into directories | 2025-10-19 | 2 | -2/+2 | |
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| * | amd64: float conversion insntrs | 2025-10-18 | 2 | -2/+43 | |
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| * | small thigns | 2025-10-18 | 1 | -1/+1 | |
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| * | codegen bugfix | 2025-10-17 | 1 | -5/+13 | |
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| * | amd64: not, udiv | 2025-10-14 | 1 | -0/+13 | |
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| * | amd64: mul -> imul | 2025-10-13 | 1 | -8/+9 | |
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| * | bugfixes | 2025-10-10 | 1 | -0/+1 | |
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| * | initial implementation of run-time array/aggregate initializers | 2025-10-08 | 1 | -0/+4 | |
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| * | fix some more codegen bugs for symbol constants | 2025-09-16 | 2 | -4/+6 | |
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| * | codegen: fix 3-address sub reg,imm codegen | 2025-09-15 | 1 | -1/+1 | |
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| * | start implementing bitfields | 2025-09-14 | 1 | -0/+6 | |
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| * | codegen: float cmp, ior; frontend: fix cond expr bug | 2025-09-14 | 2 | -5/+21 | |
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| * | preliminary pie and pic | 2025-09-14 | 2 | -19/+62 | |
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| * | regalloc: basic spilling support | 2025-09-13 | 2 | -0/+7 | |
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| * | amd64: improve codegen for ADD | 2025-09-11 | 1 | -0/+3 | |
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| * | amd64: bugfix for stack args with no RBP, also reuse epilogue code? | 2025-09-11 | 1 | -26/+48 | |
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| * | amd64/emit: fix order of stack restore operations with regs+stk | 2025-09-09 | 1 | -6/+11 | |
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| * | ioper | 2025-09-09 | 1 | -12/+21 | |
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| * | fixes, delnops | 2025-09-09 | 1 | -2/+2 | |
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| * | amd64: swap, sar | 2025-09-08 | 1 | -1/+21 | |
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| * | amd64: bugfix | 2025-09-08 | 2 | -5/+9 | |
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| * | amd64: fix isel for numeric conversion ops | 2023-08-07 | 1 | -4/+4 | |
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| * | amd64: add mulf and divf codegen | 2023-08-07 | 1 | -3/+18 | |
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| * | amd64/emit bugfix | 2023-07-09 | 1 | -3/+3 | |
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| * | amd64 codegen fixes | 2023-07-07 | 2 | -13/+20 | |
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| * | fix emit() setcc and copy | 2023-07-06 | 1 | -1/+2 | |
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| * | misc bugfixs | 2023-06-30 | 2 | -23/+92 | |
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| * | add initializers (only static for initialier list rn) | 2023-06-29 | 2 | -34/+91 | |
| | | | | | and other fixes | ||||
| * | fix some warnings | 2023-06-25 | 1 | -9/+1 | |
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| * | fix regalloc thinking some ins are dead by adding ins.keep | 2023-06-24 | 1 | -1/+5 | |
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| * | amd64/emit: more float fixes | 2023-06-24 | 1 | -21/+24 | |
| | | | | | | optimize loading 0.0 in phis as well as regular copies and also don't use inc or addr for float addition | ||||
| * | backend: don't mixup float and int temps | 2023-06-24 | 1 | -3/+3 | |
| | | | | | | | copy propagation only happens when dataclasses match, register allocator ignores hints if hint register class and instruction class differ, also add mov between int and float regs in amd64/emit | ||||
| * | backend: fix regalloc to work with more complex dataflow | 2023-06-24 | 3 | -7/+25 | |
| | | | | | | | | | basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes | ||||
| * | change RMORE -> RADDR; use RXXX (RNONE) for special args,also undef | 2023-06-22 | 2 | -26/+26 | |
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| * | explicitly store predecessors in each block | 2023-06-21 | 1 | -4/+4 | |
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| * | amd64: fix aggregate return in regs | 2023-06-20 | 1 | -3/+3 | |
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| * | amd64: conform to ABI for varargs func calls | 2023-06-20 | 2 | -1/+9 | |
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| * | improve codegen for div a little (bikeshedding) | 2023-06-20 | 1 | -0/+5 | |
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| * | amd64/emit: ensure stack is 16-byte aligned | 2023-06-20 | 1 | -10/+29 | |
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| * | fix regression wiht ret args not being fixed | 2023-06-20 | 1 | -2/+7 | |
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| * | fix out of bounds read | 2023-06-20 | 1 | -0/+1 | |
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| * | another emit() errata | 2023-06-20 | 1 | -1/+1 | |
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| * | fix regression | 2023-06-20 | 1 | -4/+4 | |
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| * | don't lower params and args to registers in abi0 | 2023-06-20 | 1 | -2/+60 | |
| | | | | | | it's better to do it later, currently in isel(), but perhaps in a pre-isel abi1 pass | ||||
| * | fix cls logic for comparison instrs | 2023-06-20 | 2 | -2/+3 | |
| | | | | | | | | | previously instr.cls always represented the output dataclass. this doesn't work for comparisons because we know the output is always a boolean integer and we care about the actual comparison dataclass. so now .cls represents the operation dataclass, which matches the result class except for comparisons where the result is always KI4V | ||||
| * | errata | 2023-06-20 | 1 | -2/+2 | |
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| * | backend: compile comparison instrs and branches | 2023-06-19 | 2 | -30/+331 | |
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| * | amd64/emit: fix mov(zx/sx)w | 2023-06-19 | 1 | -6/+6 | |
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