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* ir: only stub out float <-> u64 cvt on x86 lemon2026-01-081-4/+3
| | | | hackish..
* ir/builder: fix bug optiminzg x+x as x-x -> 0 lemon2025-12-261-2/+3
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* simpl: optimize unsigned & signed division by power of 2 lemon2025-12-211-2/+2
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* ir: simpl: optimize some constant multiplications lemon2025-12-211-7/+9
| | | | Reuse irbinop() and irunop() for the constant results cases.
* x86-64/emit: implement single-exit-point ret with jump threading lemon2025-12-161-1/+1
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* regalloc: fixbug with phi move of stack <- stack lemon2025-12-131-2/+1
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* c: make tentative definitions work lemon2025-12-021-1/+1
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* ir: simplify some occurrences of single-argument phis lemon2025-11-241-8/+7
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* ir: implement cvtu64f. and other bug fixes lemon2025-11-231-2/+35
| | | | | compiler is bootstrapping?! however, stage1 and stage2+ executables aren't bit-identical.. small differences in the codegen.. need to look into that
* implement cvtfXu64 by lowering it in builder lemon2025-11-231-9/+46
| | | | this should probably be in a separate pass?
* remove umul lemon2025-11-211-1/+1
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* change op names to match 285063eba44 lemon2025-11-211-5/+5
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* ir/builder: peephole optimize branch with constant conditional lemon2025-11-211-4/+14
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* ir: 'trap' jump; c: __builtin_trap; lex: __has_builtin lemon2025-11-151-0/+8
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* preeliminary va_list support lemon2025-11-141-4/+4
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* fold/builder: fix bad use of iscon in place of isnumcon lemon2025-11-061-4/+4
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* amd64: fix aggregate abi stuff;; ir: fold, peephole optimizing constructors lemon2025-11-051-0/+217
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