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* rega: change assert for spilled callee. it's ok if nspill==1 lemon2025-12-091-1/+1
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* abi: fix aggregate passed by regs 2nd reg offset lemon2025-12-062-24/+28
| | | | | | | | | It was broken for example `struct { i32 a; f64 b; }` (would try to load/store b from byte offset 4, not 8). Introduce r2off, realize in x86-64 it's always 8; even `struct {i32 a; f32 b;}` gets passed in one (integer) register. But not so in (future) ABIs like RISC-V, I believe there `{i32, f32}` would get passed in 1 integer and 1 float register (r2off = 4).
* add command-line predefined macros (-D, -U) lemon2025-12-061-2/+0
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* ir: float fold div/0 lemon2025-12-051-4/+3
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* regalloc: kill dead defs of physical regs lemon2025-12-041-8/+16
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* c: make tentative definitions work lemon2025-12-021-1/+1
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* abi/isel: aggregate args in stack wip lemon2025-11-271-9/+31
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* regalloc: skip dead phis lemon2025-11-261-1/+4
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* ir: simplify some occurrences of single-argument phis lemon2025-11-242-8/+17
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* ir.h: tweak mkintrin() definition to work with tinycc lemon2025-11-241-1/+1
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* ir: implement cvtu64f. and other bug fixes lemon2025-11-231-2/+35
| | | | | compiler is bootstrapping?! however, stage1 and stage2+ executables aren't bit-identical.. small differences in the codegen.. need to look into that
* implement cvtfXu64 by lowering it in builder lemon2025-11-231-9/+46
| | | | this should probably be in a separate pass?
* c: check actual reachability for non-void func may not return value lemon2025-11-232-0/+22
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* implement float varargs, and some other fixes lemon2025-11-233-7/+17
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* make sure indirect function call pointer does not end up in clobber reg lemon2025-11-221-2/+2
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* ir: freeblk: clear preds lemon2025-11-221-0/+2
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* ir/ir.c: fix assert in mkcallarg lemon2025-11-221-1/+1
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* ir/dump: initialize out buffer statically lemon2025-11-221-3/+1
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* regalloc: merge overlapping fixed intervals better lemon2025-11-221-1/+12
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* irdump: print alloca # bytes lemon2025-11-211-0/+3
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* ir: implement dominator tree computation lemon2025-11-213-0/+40
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* ir: barebones IR passes checked contracts lemon2025-11-217-2/+26
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* remove umul lemon2025-11-213-3/+1
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* change op names to match 285063eba44 lemon2025-11-218-142/+142
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* rename IR classes to reflect bitsize lemon2025-11-219-46/+46
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* regalloc: assert nops aren't being used lemon2025-11-211-0/+1
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* ir/builder: peephole optimize branch with constant conditional lemon2025-11-211-4/+14
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* mem2reg: implement marker algorithm from Braun et al lemon2025-11-211-8/+40
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* mem2reg: store pending phis implicitly lemon2025-11-211-12/+8
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* ir: fix delpred when npred becomes 1 lemon2025-11-211-2/+12
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* ir/dump: print block predecessors lemon2025-11-211-2/+10
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* cfg: sortrpo delete unreachable blocks with allocas by hoisting them to the ↵ lemon2025-11-211-6/+7
| | | | entry block
* isel: lower allocas a different way, such that stk address gets materialized ↵ lemon2025-11-201-1/+1
| | | | when necesary
* ir: for easier debugging, keep ctype in dats, print as literal when possible lemon2025-11-203-21/+53
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* mem2reg: fix edgecase.. lemon2025-11-191-1/+1
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* debug output to stdout lemon2025-11-195-75/+79
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* factor type stuff into type.h lemon2025-11-161-0/+14
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* ir: 'trap' jump; c: __builtin_trap; lex: __has_builtin lemon2025-11-154-4/+13
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* abi0: remove debugging leftover sortpo. but do number blks (free) lemon2025-11-141-1/+2
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* preeliminary va_list support lemon2025-11-146-25/+68
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* mem2reg: handle uses in branches in cmpuse() lemon2025-11-121-0/+2
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* ir: fix addcon equality check.. lemon2025-11-121-1/+1
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* revert b55005e5c08. correct fix was in c.c lemon2025-11-121-1/+0
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* fold: clamp int to 32bits when required lemon2025-11-121-0/+1
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* mem2reg: sort variable uses to match source order.. lemon2025-11-121-0/+21
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* ir: free uses lemon2025-11-121-0/+4
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* irdump: don't print fn ret type in non return branches lemon2025-11-121-1/+1
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* implement argument passing in stack lemon2025-11-122-0/+2
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* fixup! amd64: get rid of xinc/xdec. handle those at emit stage lemon2025-11-091-0/+1
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* amd64: get rid of xinc/xdec. handle those at emit stage lemon2025-11-091-2/+0
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