| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ir: bump MAXINSTR | 2025-12-10 | 1 | -1/+1 | |
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| * | parallel move; implement reg<->stack swp | 2025-12-10 | 1 | -3/+18 | |
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| * | regalloc: optimize a little edge case better | 2025-12-10 | 1 | -4/+6 | |
| | | | | | | | | | | | | | With two-address instructions one needs to make sure the dst doesn't get allocated to the same reg as the right-hand operand: %r = mul %x, %y ; %y cannot be %r Except, if the operands are the same %r = mul %x, %x ; if %x is dead after this instr, it's fine to allocate %r to the same reg | ||||
| * | misc fixes | 2025-12-10 | 1 | -1/+1 | |
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| * | rega: change assert for spilled callee. it's ok if nspill==1 | 2025-12-09 | 1 | -1/+1 | |
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| * | abi: fix aggregate passed by regs 2nd reg offset | 2025-12-06 | 2 | -24/+28 | |
| | | | | | | | | | | It was broken for example `struct { i32 a; f64 b; }` (would try to load/store b from byte offset 4, not 8). Introduce r2off, realize in x86-64 it's always 8; even `struct {i32 a; f32 b;}` gets passed in one (integer) register. But not so in (future) ABIs like RISC-V, I believe there `{i32, f32}` would get passed in 1 integer and 1 float register (r2off = 4). | ||||
| * | add command-line predefined macros (-D, -U) | 2025-12-06 | 1 | -2/+0 | |
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| * | ir: float fold div/0 | 2025-12-05 | 1 | -4/+3 | |
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| * | regalloc: kill dead defs of physical regs | 2025-12-04 | 1 | -8/+16 | |
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| * | c: make tentative definitions work | 2025-12-02 | 1 | -1/+1 | |
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| * | abi/isel: aggregate args in stack wip | 2025-11-27 | 1 | -9/+31 | |
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| * | regalloc: skip dead phis | 2025-11-26 | 1 | -1/+4 | |
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| * | ir: simplify some occurrences of single-argument phis | 2025-11-24 | 2 | -8/+17 | |
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| * | ir.h: tweak mkintrin() definition to work with tinycc | 2025-11-24 | 1 | -1/+1 | |
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| * | ir: implement cvtu64f. and other bug fixes | 2025-11-23 | 1 | -2/+35 | |
| | | | | | | compiler is bootstrapping?! however, stage1 and stage2+ executables aren't bit-identical.. small differences in the codegen.. need to look into that | ||||
| * | implement cvtfXu64 by lowering it in builder | 2025-11-23 | 1 | -9/+46 | |
| | | | | | this should probably be in a separate pass? | ||||
| * | c: check actual reachability for non-void func may not return value | 2025-11-23 | 2 | -0/+22 | |
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| * | implement float varargs, and some other fixes | 2025-11-23 | 3 | -7/+17 | |
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| * | make sure indirect function call pointer does not end up in clobber reg | 2025-11-22 | 1 | -2/+2 | |
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| * | ir: freeblk: clear preds | 2025-11-22 | 1 | -0/+2 | |
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| * | ir/ir.c: fix assert in mkcallarg | 2025-11-22 | 1 | -1/+1 | |
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| * | ir/dump: initialize out buffer statically | 2025-11-22 | 1 | -3/+1 | |
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| * | regalloc: merge overlapping fixed intervals better | 2025-11-22 | 1 | -1/+12 | |
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| * | irdump: print alloca # bytes | 2025-11-21 | 1 | -0/+3 | |
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| * | ir: implement dominator tree computation | 2025-11-21 | 3 | -0/+40 | |
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| * | ir: barebones IR passes checked contracts | 2025-11-21 | 7 | -2/+26 | |
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| * | remove umul | 2025-11-21 | 3 | -3/+1 | |
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| * | change op names to match 285063eba44 | 2025-11-21 | 8 | -142/+142 | |
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| * | rename IR classes to reflect bitsize | 2025-11-21 | 9 | -46/+46 | |
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| * | regalloc: assert nops aren't being used | 2025-11-21 | 1 | -0/+1 | |
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| * | ir/builder: peephole optimize branch with constant conditional | 2025-11-21 | 1 | -4/+14 | |
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| * | mem2reg: implement marker algorithm from Braun et al | 2025-11-21 | 1 | -8/+40 | |
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| * | mem2reg: store pending phis implicitly | 2025-11-21 | 1 | -12/+8 | |
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| * | ir: fix delpred when npred becomes 1 | 2025-11-21 | 1 | -2/+12 | |
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| * | ir/dump: print block predecessors | 2025-11-21 | 1 | -2/+10 | |
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| * | cfg: sortrpo delete unreachable blocks with allocas by hoisting them to the ↵ | 2025-11-21 | 1 | -6/+7 | |
| | | | | | entry block | ||||
| * | isel: lower allocas a different way, such that stk address gets materialized ↵ | 2025-11-20 | 1 | -1/+1 | |
| | | | | | when necesary | ||||
| * | ir: for easier debugging, keep ctype in dats, print as literal when possible | 2025-11-20 | 3 | -21/+53 | |
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| * | mem2reg: fix edgecase.. | 2025-11-19 | 1 | -1/+1 | |
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| * | debug output to stdout | 2025-11-19 | 5 | -75/+79 | |
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| * | factor type stuff into type.h | 2025-11-16 | 1 | -0/+14 | |
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| * | ir: 'trap' jump; c: __builtin_trap; lex: __has_builtin | 2025-11-15 | 4 | -4/+13 | |
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| * | abi0: remove debugging leftover sortpo. but do number blks (free) | 2025-11-14 | 1 | -1/+2 | |
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| * | preeliminary va_list support | 2025-11-14 | 6 | -25/+68 | |
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| * | mem2reg: handle uses in branches in cmpuse() | 2025-11-12 | 1 | -0/+2 | |
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| * | ir: fix addcon equality check.. | 2025-11-12 | 1 | -1/+1 | |
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| * | revert b55005e5c08. correct fix was in c.c | 2025-11-12 | 1 | -1/+0 | |
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| * | fold: clamp int to 32bits when required | 2025-11-12 | 1 | -0/+1 | |
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| * | mem2reg: sort variable uses to match source order.. | 2025-11-12 | 1 | -0/+21 | |
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| * | ir: free uses | 2025-11-12 | 1 | -0/+4 | |
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