| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rega: move bssize | 2025-10-08 | 1 | -3/+2 | |
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| * | rega: don't make fixed intervals for globally live regs | 2025-10-07 | 1 | -1/+4 | |
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| * | alloc changes | 2025-09-17 | 1 | -7/+2 | |
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| * | mem2reg: fix deltrivialphis bug | 2025-09-15 | 1 | -0/+1 | |
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| * | regalloc: hand-roll qsort (bikeshedding...) | 2025-09-15 | 1 | -9/+31 | |
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| * | a little refactoring and cleanup | 2025-09-15 | 1 | -248/+211 | |
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| * | regalloc move things around | 2025-09-15 | 1 | -80/+80 | |
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| * | regset doesnt need all those macros | 2025-09-14 | 1 | -16/+16 | |
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| * | regalloc.c cleanup | 2025-09-14 | 1 | -187/+204 | |
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| * | change freearena for correctness | 2025-09-14 | 1 | -1/+0 | |
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| * | regalloc: free stk slots | 2025-09-14 | 1 | -5/+15 | |
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| * | regalloc improvements | 2025-09-14 | 1 | -33/+50 | |
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| * | regalloc: basic spilling support | 2025-09-13 | 1 | -37/+136 | |
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| * | regalloc: prepare for spilling logic.. | 2025-09-13 | 1 | -152/+145 | |
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| * | fixes, delnops | 2025-09-09 | 1 | -1/+1 | |
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| * | regalloc: start implementing linear scan | 2025-09-08 | 1 | -438/+591 | |
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| * | hm | 2023-08-07 | 1 | -4/+4 | |
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| * | regalloc fixes and rpo | 2023-07-09 | 1 | -10/+55 | |
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| * | regalloc: update preds during simplify pass | 2023-07-07 | 1 | -1/+7 | |
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| * | misc bugfixs | 2023-06-30 | 1 | -5/+6 | |
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| * | regalloc: remove unused variable | 2023-06-26 | 1 | -5/+0 | |
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| * | backend: fix mem2reg & regalloc | 2023-06-26 | 1 | -31/+155 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | they were broken, especially for unstructured control flow. most significant fix is to register allocator for temporaries that are used before the first definition in the source order, e.g.: @1: %x = add %y, 1 b @3 @2 %y = ... b @1 it's legal for %x to use %y there (assuming @2 dominates @1) but from the point of view of the register allocator %y is defined and freed and then used again, which broke things. the fix is to introduce phis for this situation: @1: %y.1 = phi @2 %y %x = add %y.1, 1 b @3 @2 %y = ... b @1 then regalloc phi handling code makes it work | ||||
| * | regalloc: fix temporary rename clobbering return register with multiple returns | 2023-06-25 | 1 | -2/+13 | |
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| * | regalloc add sources | 2023-06-25 | 1 | -1/+3 | |
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| * | fix regalloc thinking some ins are dead by adding ins.keep | 2023-06-24 | 1 | -1/+1 | |
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| * | backend: don't mixup float and int temps | 2023-06-24 | 1 | -5/+6 | |
| | | | | | | | copy propagation only happens when dataclasses match, register allocator ignores hints if hint register class and instruction class differ, also add mov between int and float regs in amd64/emit | ||||
| * | backend: fix regalloc to work with more complex dataflow | 2023-06-24 | 1 | -190/+556 | |
| | | | | | | | | | basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes | ||||
| * | change RMORE -> RADDR; use RXXX (RNONE) for special args,also undef | 2023-06-22 | 1 | -15/+15 | |
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| * | explicitly store predecessors in each block | 2023-06-21 | 1 | -5/+5 | |
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| * | improve codegen for div a little (bikeshedding) | 2023-06-20 | 1 | -1/+2 | |
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| * | amd64/emit: ensure stack is 16-byte aligned | 2023-06-20 | 1 | -0/+4 | |
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| * | add basic mem2reg | 2023-06-20 | 1 | -12/+17 | |
| | | | | | | | | promotes uniform stack slots to temporaries currently only for immutable variables, next thing to implement is ssa construction | ||||
| * | regalloc: fix bug in spilling code | 2023-06-20 | 1 | -7/+24 | |
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| * | don't lower params and args to registers in abi0 | 2023-06-20 | 1 | -1/+1 | |
| | | | | | | it's better to do it later, currently in isel(), but perhaps in a pre-isel abi1 pass | ||||
| * | fix cls logic for comparison instrs | 2023-06-20 | 1 | -8/+8 | |
| | | | | | | | | | previously instr.cls always represented the output dataclass. this doesn't work for comparisons because we know the output is always a boolean integer and we care about the actual comparison dataclass. so now .cls represents the operation dataclass, which matches the result class except for comparisons where the result is always KI4V | ||||
| * | regalloc: alloc extra memory for alloc map | 2023-06-19 | 1 | -1/+1 | |
| | | | | | | regalloc itself can insert instructions so this was causing out of bounds read errors | ||||
| * | backend: compile comparison instrs and branches | 2023-06-19 | 1 | -1/+6 | |
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| * | hint in-place operations to use same reg for lhs and dest | 2023-06-15 | 1 | -1/+1 | |
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| * | less memset | 2023-06-15 | 1 | -1/+0 | |
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| * | cleanup | 2023-06-14 | 1 | -15/+14 | |
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| * | add spilling for function calls, misc fixes | 2023-06-14 | 1 | -22/+140 | |
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| * | use a hashtable for addr refs | 2023-06-13 | 1 | -3/+4 | |
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| * | lower allocas in isel() instead of emit() and misc fixes | 2023-06-13 | 1 | -17/+20 | |
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| * | dec,inc,sub | 2023-06-12 | 1 | -0/+1 | |
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| * | bugfix | 2023-06-12 | 1 | -2/+3 | |
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| * | something with phi | 2023-06-12 | 1 | -29/+15 | |
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| * | register renaming and such | 2023-06-12 | 1 | -35/+147 | |
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| * | remove RPARAM, add Oparam, lower args/rets to abi regs in abi0 | 2023-06-11 | 1 | -21/+5 | |
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| * | isel skeleton | 2023-06-10 | 1 | -4/+21 | |
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| * | regalloc: lower phis | 2023-06-05 | 1 | -5/+26 | |
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