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* fix some warnings lemon2023-06-251-1/+0
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* backend: don't mixup float and int temps lemon2023-06-241-3/+9
| | | | | | copy propagation only happens when dataclasses match, register allocator ignores hints if hint register class and instruction class differ, also add mov between int and float regs in amd64/emit
* backend: fix regalloc to work with more complex dataflow lemon2023-06-241-0/+23
| | | | | | | | basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes
* change RMORE -> RADDR; use RXXX (RNONE) for special args,also undef lemon2023-06-221-2/+0
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* mem2reg: implement ssa construction; this breaks regalloc right now lemon2023-06-211-68/+11
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* explicitly store predecessors in each block lemon2023-06-211-3/+3
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* add basic mem2reg lemon2023-06-201-0/+89
promotes uniform stack slots to temporaries currently only for immutable variables, next thing to implement is ssa construction