From 19bbdfa3c7ae05f4694ce5e434d9855c6f2c3682 Mon Sep 17 00:00:00 2001 From: lemon Date: Sat, 24 Jun 2023 18:47:05 +0200 Subject: backend: fix regalloc to work with more complex dataflow basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes --- amd64/isel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'amd64/isel.c') diff --git a/amd64/isel.c b/amd64/isel.c index cb87b7d..07115ac 100644 --- a/amd64/isel.c +++ b/amd64/isel.c @@ -187,7 +187,7 @@ aadd(struct addr *addr, union ref r) } else if (r.t == RREG) { /* temporaries are single assignment, but register aren't, so they can't be * * safely hoisted into an address value, unless they have global lifetime */ - if (!bstest(mctarg->rglob, r.i)) return 0; + if (!rstest(mctarg->rglob, r.i)) return 0; Ref: if (!addr->base.bits) addr->base = r; else if (!addr->index.bits) addr->index = r; -- cgit v1.2.3