From c0db7d92c14b242daf008f7e3731a5d080e23fa1 Mon Sep 17 00:00:00 2001 From: lemon Date: Sat, 28 Feb 2026 09:12:18 +0100 Subject: regalloc: fix defn of spilled var with immediate With `i64 %a = copy 0xabcdef12345`, if `%a` was spilled, this would turn into a `storei64` instruction with an unencondable immediate operand (larger than 32 bits in x86, non-zero in aarch64). --- ir/regalloc.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'ir/regalloc.c') diff --git a/ir/regalloc.c b/ir/regalloc.c index 85b6a65..aa18e10 100644 --- a/ir/regalloc.c +++ b/ir/regalloc.c @@ -1033,6 +1033,19 @@ linearscan(struct rega *ra) DBG("\n"); } +static bool +isstoreimm(union ref r) +{ + if (r.t == RTMP) return 1; /* register OK */ + if (isintcon(r)) switch (target.arch) { + case ISxxx: assert(0); + /* TODO don't hard code this architecture dependent dispatch */ + case ISx86_64: return concls(r) == KI32; /* x86: MOV [addr], imm32 */ + case ISaarch64: return r.i == 0; /* arm doesn't have STR , but has zero register */ + } + return 0; +} + /* replace temps with physical regs, add loads & stores for spilled temps */ static bool devirt(struct rega *ra, struct block *blk) @@ -1139,7 +1152,7 @@ devirt(struct rega *ra, struct block *blk) enum irclass cls = insrescls(*ins); int store = cls2store[cls]; /* t was spilled, gen store */ - if (ins->op == Ocopy && ins->l.t != RADDR && !isaddrcon(ins->l,0)) { + if (ins->op == Ocopy && isstoreimm(ins->l)) { ins->op = store; ins->r = ins->l; addstkslotref(temp, alloc->a*8); -- cgit v1.2.3