From f13b3021eb273af3093a498fb3b09271546ae3cc Mon Sep 17 00:00:00 2001 From: lemon Date: Sun, 12 Apr 2026 11:49:17 +0200 Subject: aarch64: fix stack frame layout, again Turns out hardware enforces SP 16-bit alignment in every SP relative load/store, but QEMU doesn't emulate this. --- src/t_aarch64_isel.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/t_aarch64_isel.c') diff --git a/src/t_aarch64_isel.c b/src/t_aarch64_isel.c index 178fa23..1d49012 100644 --- a/src/t_aarch64_isel.c +++ b/src/t_aarch64_isel.c @@ -264,6 +264,10 @@ aadd(IRAddr *addr, Block *blk, int *curi, Ref r, uint siz/*1,2,4,8*/) if (r.t == RSTACK) { if (addr->base.bits) goto Ref; addr->base = r; + } else if (r.t == RADDR) { + if (!addr->base.bits && !addr->index.bits && !addr->disp) { + *addr = addrtab.p[r.i]; + } else goto Ref; } else if (r.t == RTMP) { Instr *ins = &instrtab[r.i]; if (ins->op == Oadd) { @@ -534,6 +538,7 @@ seljmp(Function *fn, Block *blk) if (blk->jmp.arg[1].bits) { r = mkref(RREG, fn->abiret[1].reg); ins = &instrtab[insertinstr(blk, blk->ins.n, mkinstr2(Omove, fn->abiret[1].ty.cls, r, blk->jmp.arg[1])).i]; + blk->jmp.arg[1] = r; } } } -- cgit v1.2.3