| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | ioper | 2025-09-09 | 1 | -12/+21 | ||
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| * | fixes, delnops | 2025-09-09 | 1 | -2/+2 | ||
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| * | amd64: swap, sar | 2025-09-08 | 1 | -1/+21 | ||
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| * | amd64: bugfix | 2025-09-08 | 1 | -4/+9 | ||
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| * | amd64: add mulf and divf codegen | 2023-08-07 | 1 | -3/+18 | ||
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| * | amd64/emit bugfix | 2023-07-09 | 1 | -3/+3 | ||
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| * | amd64 codegen fixes | 2023-07-07 | 1 | -12/+19 | ||
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| * | fix emit() setcc and copy | 2023-07-06 | 1 | -1/+2 | ||
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| * | misc bugfixs | 2023-06-30 | 1 | -19/+90 | ||
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| * | add initializers (only static for initialier list rn) | 2023-06-29 | 1 | -27/+58 | ||
| | | | | | and other fixes | |||||
| * | backend: don't mixup float and int temps | 2023-06-24 | 1 | -3/+3 | ||
| | | | | | | | copy propagation only happens when dataclasses match, register allocator ignores hints if hint register class and instruction class differ, also add mov between int and float regs in amd64/emit | |||||
| * | backend: fix regalloc to work with more complex dataflow | 2023-06-24 | 1 | -4/+22 | ||
| | | | | | | | | | basically an allocation map at the beginning (in) and end (out) of each block is kept and after the first allocation pass another pass is ran to resolve allocation conflicts between each edge, plus another pass to finish lowering phi functions. also introduced `regset` and plenty of other miscellaneous fixes | |||||
| * | change RMORE -> RADDR; use RXXX (RNONE) for special args,also undef | 2023-06-22 | 1 | -14/+14 | ||
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| * | amd64: conform to ABI for varargs func calls | 2023-06-20 | 1 | -0/+9 | ||
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| * | amd64/emit: ensure stack is 16-byte aligned | 2023-06-20 | 1 | -10/+29 | ||
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| * | another emit() errata | 2023-06-20 | 1 | -1/+1 | ||
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| * | fix regression | 2023-06-20 | 1 | -4/+4 | ||
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| * | fix cls logic for comparison instrs | 2023-06-20 | 1 | -1/+2 | ||
| | | | | | | | | | previously instr.cls always represented the output dataclass. this doesn't work for comparisons because we know the output is always a boolean integer and we care about the actual comparison dataclass. so now .cls represents the operation dataclass, which matches the result class except for comparisons where the result is always KI4V | |||||
| * | errata | 2023-06-20 | 1 | -2/+2 | ||
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| * | backend: compile comparison instrs and branches | 2023-06-19 | 1 | -14/+229 | ||
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| * | amd64/emit: fix mov(zx/sx)w | 2023-06-19 | 1 | -6/+6 | ||
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| * | fix isel & emit for sym constants | 2023-06-19 | 1 | -1/+4 | ||
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| * | oops | 2023-06-19 | 1 | -1/+1 | ||
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| * | add endian.h for endian dependent stuff | 2023-06-18 | 1 | -0/+1 | ||
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| * | basic ELF output | 2023-06-17 | 1 | -7/+29 | ||
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| * | misc | 2023-06-17 | 1 | -10/+14 | ||
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| * | oops | 2023-06-14 | 1 | -1/+1 | ||
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| * | imrpove emit() | 2023-06-14 | 1 | -78/+104 | ||
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| * | add spilling for function calls, misc fixes | 2023-06-14 | 1 | -6/+18 | ||
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| * | simpler handling of large constants in IR | 2023-06-14 | 1 | -4/+4 | ||
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| * | use a hashtable for addr refs | 2023-06-13 | 1 | -2/+2 | ||
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| * | lower allocas in isel() instead of emit() and misc fixes | 2023-06-13 | 1 | -47/+8 | ||
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| * | amd64/emit: add comments | 2023-06-12 | 1 | -87/+115 | ||
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| * | dumb | 2023-06-12 | 1 | -9/+8 | ||
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| * | xor reg,reg | 2023-06-12 | 1 | -3/+13 | ||
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| * | nyi fdiv | 2023-06-12 | 1 | -1/+1 | ||
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| * | dec,inc,sub | 2023-06-12 | 1 | -0/+22 | ||
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| * | amd64/emit: emit LEA for 3-address ADD | 2023-06-12 | 1 | -3/+14 | ||
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| * | register renaming and such | 2023-06-12 | 1 | -3/+27 | ||
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| * | remove RPARAM, add Oparam, lower args/rets to abi regs in abi0 | 2023-06-11 | 1 | -32/+62 | ||
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| * | isel skeleton | 2023-06-10 | 1 | -114/+344 | ||
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| * | codegen skeleton | 2023-06-06 | 1 | -0/+323 | ||
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