| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | rega: fix spill copy of i32 -> i64 | 2026-01-04 | 1 | -4/+4 | |
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| * | backend: separate instrs for integer/float store | 2025-12-31 | 1 | -3/+3 | |
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| * | ir: use BIT macro for regset (1<< is wrong for u64) | 2025-12-23 | 1 | -6/+6 | |
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| * | rega: fix 3ff0bfcb | 2025-12-21 | 1 | -4/+1 | |
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| * | rega: fix infinite loop when compiling infinite loop | 2025-12-20 | 1 | -1/+4 | |
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| * | backend: unify pass memory allocation strategies | 2025-12-20 | 1 | -1/+1 | |
| | | | | | | | It was all over the place for temporary data structures used by individual passes. Now there is an arena specifically for that, which is nicer. | ||||
| * | ir/regalloc: struct alloc -> union alloc | 2025-12-20 | 1 | -16/+15 | |
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| * | ir: move cls2load to interface | 2025-12-18 | 1 | -4/+0 | |
| | | | | | | There's plenty of code duplication like this around I'm looking to reduce. | ||||
| * | regalloc+emit: get rid of xsave/xrestore hack | 2025-12-18 | 1 | -49/+63 | |
| | | | | | | | | Was used for situation where we needed to spill more than 1 temporary and have to use a register that is already used. Instead of push/pop, we can just allocate and set aside specific stack slots for this purpose. Also, reworked linearscan() interval sets to separate FPR/GPR intervals. | ||||
| * | rega: implement stack<->stack swap for parallel moves | 2025-12-18 | 1 | -29/+34 | |
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| * | x86_64: for vararg calls, write to EAX in isel | 2025-12-18 | 1 | -8/+25 | |
| | | | | | Also, in regalloc ensure fixed intervals are sorted | ||||
| * | x86-64/emit: implement single-exit-point ret with jump threading | 2025-12-16 | 1 | -0/+2 | |
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| * | bitset: better implementation of bsiter() and stuff | 2025-12-16 | 1 | -1/+1 | |
| | | | | | Also changed the type to size_t for portability | ||||
| * | regalloc: fix lifetime construction for nested loops | 2025-12-15 | 1 | -17/+34 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, given something like ``` 1 a = ... 2 loop { // outer 3 b = do something with a 4 loop { // inner 5 ... 6 if (b < 0) 7 break 'inner; 8 if (b == 0) 9 return; 10 ... 11 } 12 } ``` Regalloc thought outer goes from 2..6, because 6 is the last place where flow jumps directly back to 2. So `a` would have the lifetime [1,7). However if neither the break nor return are taken, the inner loop repeats and then control could flow back to 7 -> 3. But now the physical location for `a` might have been clobbered between 8..10, which is wrong. This fixes that by making sure the outer loop is considered to span 2..10. The way I went about it might not be the best way of doing it. I'm not 100% certain that it's fully correct and will always find the correct loopend, either. It's surprising it took this long to hit this edge case. | ||||
| * | regalloc: fixbug with phi move of stack <- stack | 2025-12-13 | 1 | -4/+4 | |
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| * | rename arraylength macro -> countof | 2025-12-11 | 1 | -2/+2 | |
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| * | parallel move; implement reg<->stack swp | 2025-12-10 | 1 | -3/+18 | |
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| * | regalloc: optimize a little edge case better | 2025-12-10 | 1 | -4/+6 | |
| | | | | | | | | | | | | | With two-address instructions one needs to make sure the dst doesn't get allocated to the same reg as the right-hand operand: %r = mul %x, %y ; %y cannot be %r Except, if the operands are the same %r = mul %x, %x ; if %x is dead after this instr, it's fine to allocate %r to the same reg | ||||
| * | misc fixes | 2025-12-10 | 1 | -1/+1 | |
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| * | rega: change assert for spilled callee. it's ok if nspill==1 | 2025-12-09 | 1 | -1/+1 | |
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| * | regalloc: kill dead defs of physical regs | 2025-12-04 | 1 | -8/+16 | |
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| * | regalloc: skip dead phis | 2025-11-26 | 1 | -1/+4 | |
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| * | implement float varargs, and some other fixes | 2025-11-23 | 1 | -5/+12 | |
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| * | make sure indirect function call pointer does not end up in clobber reg | 2025-11-22 | 1 | -2/+2 | |
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| * | regalloc: merge overlapping fixed intervals better | 2025-11-22 | 1 | -1/+12 | |
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| * | ir: barebones IR passes checked contracts | 2025-11-21 | 1 | -0/+2 | |
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| * | change op names to match 285063eba44 | 2025-11-21 | 1 | -11/+11 | |
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| * | rename IR classes to reflect bitsize | 2025-11-21 | 1 | -5/+5 | |
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| * | regalloc: assert nops aren't being used | 2025-11-21 | 1 | -0/+1 | |
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| * | debug output to stdout | 2025-11-19 | 1 | -2/+2 | |
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| * | ir: 'trap' jump; c: __builtin_trap; lex: __has_builtin | 2025-11-15 | 1 | -2/+2 | |
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| * | amd64: fix aggregate abi stuff;; ir: fold, peephole optimizing constructors | 2025-11-05 | 1 | -6/+13 | |
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| * | regalloc: misc | 2025-11-02 | 1 | -3/+3 | |
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| * | rega: fix parallel stack moves | 2025-11-02 | 1 | -6/+19 | |
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| * | rega: fix Ocopy of stk->stk | 2025-10-26 | 1 | -3/+2 | |
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| * | regalloc: fix spill edge case again | 2025-10-24 | 1 | -1/+5 | |
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| * | ir bugfixes | 2025-10-23 | 1 | -2/+2 | |
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| * | regalloc: implement spilling output when 1 input was spilled | 2025-10-23 | 1 | -5/+21 | |
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| * | fix edge case codegen bugs (w/ stack offsets, spilling) | 2025-10-22 | 1 | -6/+13 | |
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| * | always keep volatile loads | 2025-10-22 | 1 | -0/+4 | |
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| * | regalloc fix devirt | 2025-10-22 | 1 | -3/+5 | |
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| * | codegen bugfixes | 2025-10-19 | 1 | -3/+7 | |
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| * | Organize source files into directories | 2025-10-19 | 1 | -0/+1195 | |
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