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* REFACTOR: move sources to src/lemon2026-03-171-1417/+0
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* regalloc: improve spilling and cleanuplemon2026-03-161-347/+393
| | | | | | | | Instead of spilling current interval when running out of registers, spill the longest-lived active interval with a lower spill cost than current. Spill costs are estimated based on multiplicative loop depth. Also cleanup regalloc.c somewhat. Update todo.txt too.
* regalloc: fix minor regression with storing of regs into spilled stack slotslemon2026-03-041-1/+1
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* ir: make address ref hash table resizablelemon2026-02-281-5/+12
| | | | Would hit the limit on very large functions (thanks csmith).
* regalloc: fix defn of spilled var with immediatelemon2026-02-281-1/+14
| | | | | | With `i64 %a = copy 0xabcdef12345`, if `%a` was spilled, this would turn into a `storei64` instruction with an unencondable immediate operand (larger than 32 bits in x86, non-zero in aarch64).
* ir: regalloc & x86-64 isel bugfixeslemon2026-02-181-1/+1
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* codegen: eliminate redudant consecutive ret sequenceslemon2026-01-081-0/+1
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* rega: fix spill copy of i32 -> i64lemon2026-01-041-4/+4
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* backend: separate instrs for integer/float storelemon2025-12-311-3/+3
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* ir: use BIT macro for regset (1<< is wrong for u64)lemon2025-12-231-6/+6
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* rega: fix 3ff0bfcblemon2025-12-211-4/+1
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* rega: fix infinite loop when compiling infinite looplemon2025-12-201-1/+4
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* backend: unify pass memory allocation strategieslemon2025-12-201-1/+1
| | | | | | It was all over the place for temporary data structures used by individual passes. Now there is an arena specifically for that, which is nicer.
* ir/regalloc: struct alloc -> union alloclemon2025-12-201-16/+15
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* ir: move cls2load to interfacelemon2025-12-181-4/+0
| | | | | There's plenty of code duplication like this around I'm looking to reduce.
* regalloc+emit: get rid of xsave/xrestore hacklemon2025-12-181-49/+63
| | | | | | | Was used for situation where we needed to spill more than 1 temporary and have to use a register that is already used. Instead of push/pop, we can just allocate and set aside specific stack slots for this purpose. Also, reworked linearscan() interval sets to separate FPR/GPR intervals.
* rega: implement stack<->stack swap for parallel moveslemon2025-12-181-29/+34
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* x86_64: for vararg calls, write to EAX in isellemon2025-12-181-8/+25
| | | | Also, in regalloc ensure fixed intervals are sorted
* x86-64/emit: implement single-exit-point ret with jump threadinglemon2025-12-161-0/+2
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* bitset: better implementation of bsiter() and stufflemon2025-12-161-1/+1
| | | | Also changed the type to size_t for portability
* regalloc: fix lifetime construction for nested loopslemon2025-12-151-17/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, given something like ``` 1 a = ... 2 loop { // outer 3 b = do something with a 4 loop { // inner 5 ... 6 if (b < 0) 7 break 'inner; 8 if (b == 0) 9 return; 10 ... 11 } 12 } ``` Regalloc thought outer goes from 2..6, because 6 is the last place where flow jumps directly back to 2. So `a` would have the lifetime [1,7). However if neither the break nor return are taken, the inner loop repeats and then control could flow back to 7 -> 3. But now the physical location for `a` might have been clobbered between 8..10, which is wrong. This fixes that by making sure the outer loop is considered to span 2..10. The way I went about it might not be the best way of doing it. I'm not 100% certain that it's fully correct and will always find the correct loopend, either. It's surprising it took this long to hit this edge case.
* regalloc: fixbug with phi move of stack <- stacklemon2025-12-131-4/+4
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* rename arraylength macro -> countoflemon2025-12-111-2/+2
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* parallel move; implement reg<->stack swplemon2025-12-101-3/+18
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* regalloc: optimize a little edge case betterlemon2025-12-101-4/+6
| | | | | | | | | | | | With two-address instructions one needs to make sure the dst doesn't get allocated to the same reg as the right-hand operand: %r = mul %x, %y ; %y cannot be %r Except, if the operands are the same %r = mul %x, %x ; if %x is dead after this instr, it's fine to allocate %r to the same reg
* misc fixeslemon2025-12-101-1/+1
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* rega: change assert for spilled callee. it's ok if nspill==1lemon2025-12-091-1/+1
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* regalloc: kill dead defs of physical regslemon2025-12-041-8/+16
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* regalloc: skip dead phislemon2025-11-261-1/+4
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* implement float varargs, and some other fixeslemon2025-11-231-5/+12
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* make sure indirect function call pointer does not end up in clobber reglemon2025-11-221-2/+2
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* regalloc: merge overlapping fixed intervals betterlemon2025-11-221-1/+12
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* ir: barebones IR passes checked contractslemon2025-11-211-0/+2
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* change op names to match 285063eba44lemon2025-11-211-11/+11
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* rename IR classes to reflect bitsizelemon2025-11-211-5/+5
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* regalloc: assert nops aren't being usedlemon2025-11-211-0/+1
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* debug output to stdoutlemon2025-11-191-2/+2
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* ir: 'trap' jump; c: __builtin_trap; lex: __has_builtinlemon2025-11-151-2/+2
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* amd64: fix aggregate abi stuff;; ir: fold, peephole optimizing constructorslemon2025-11-051-6/+13
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* regalloc: misclemon2025-11-021-3/+3
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* rega: fix parallel stack moveslemon2025-11-021-6/+19
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* rega: fix Ocopy of stk->stklemon2025-10-261-3/+2
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* regalloc: fix spill edge case againlemon2025-10-241-1/+5
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* ir bugfixeslemon2025-10-231-2/+2
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* regalloc: implement spilling output when 1 input was spilledlemon2025-10-231-5/+21
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* fix edge case codegen bugs (w/ stack offsets, spilling)lemon2025-10-221-6/+13
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* always keep volatile loadslemon2025-10-221-0/+4
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* regalloc fix devirtlemon2025-10-221-3/+5
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* codegen bugfixeslemon2025-10-191-3/+7
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* Organize source files into directorieslemon2025-10-191-0/+1195
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